Semiconductor device structures have been made with increased storage and logic density, primarily by reducing the lateral dimensions of the devices and conducting patterns which form the circuits. However, there is a limit to how small devices and patterns can be made, and how closely the devices can be packed. In particular, heat dissipation may be a limiting factor in the ultimate device and circuit density that can be achieved. IIn order to avoid the constraints related to decreasing the size of devices and packing them more closely together, scientists have been considering the possibility of three dimensional (3D ) structures wherein the storage or logic capacity of a structure can be increased by utilizing a vertical dimension, in addition to lateral dimensions. To accomplish these ends, scientists have considered many different types of semiconductor homostructures and heterostructures, i.e., combinations of layers of different semiconductor materials in a single composite crystal. Structures of this type would provide an increased number of selection criteria to device designers, including electrical properties which may or may not be present in structures utilizing only two dimensions.
Semiconductor 3D heterostructures or homostructures having perfection suitable for state of the art devices are extremely difficult to produce. Many approaches have been utilized, including the combination of III-V materials, or the combination of II-VI semiconductors. These III-V or II-VI semiconductors have been proposed in combination with ternery materials in the same systems including, for example, GaAs and GaAlAs. Layers having slightly different amounts of the ternery addition can be compositionally graded to reduce the effect of the top positional discontinuity. These structures are used in optoelectronic devices, and have been proposed for other uses.
An example of a heterostructure incorporating a metal layer is found in U.S. Pat. No. 4,492,971. In this reference, a three layer semiconductor heterostructure is described which incorporates a metal silicide layer. A substrate comprised of a single crystal of silicon has an overlying layer of a single crystal metal silicide. This metal silicide has a crystalline perfection very similar to that of the underlying single crystal silicon. Because of this, an overlying layer of silicon can be formed on the metal silicide layer in order to complete the 3-dimensional structure. Also, the overlying layer can be a material other than silicon as long as that material is one which is capable of growing epitaxially on the metal silicide.
The 3-dimensional structure illustrated in the aforementioned patent is one which is comprised of three distinct layers. It is not possible using the techniques of that reference to have the silicide layer formed within the underlying single crystal semiconductor layer in a manner to provide a planar top surface including silicide regions and the single crystal semiconductor. This is particularly true if the metal silicide is patterned, rather than being laterally coextensive with the underlying silicon layer. This lack of planarization when a patterned silicide layer is formed will occur regardless of the technique used to form the metal silicide layer. Thus, the structure of this reference always includes three distinct layers, one of which is the metal silicide layer.
It would be desireable to form a 3-dimensional semiconductor structure in which the surface of the metal silicide regions is coextensive with the surface of the single crystal silicon layer, i.e., one in which the metal silicide regions are embedded in the single crystal silicon layer in a manner such that a planar top surface is provided. In order to have complete planarization so that the subsequently formed overlying semiconductor layer is perfectly planar, there can be no step, or surface irregularity, in the areas where the metal silicide is formed. Such total planarization cannot be achieved using the technique of U.S. Pat. No. 4,492,971.
Whenever a layer of a silicide-forming metal is deposited on a silicon layer and subsequently annealed to form a metal silicide, the metal silicide will grow both into the silicon layer and out from the silicon layer. If the out-growing, or protruding, portion of the metal silicide is to be removed in order to leave a planar surface, this can be achieved only by disadvantageous mechanical-type polishing steps. Any type of reactive etching, including reactive ion etching and chemical etching, will attack and remove both the protruding silicide region and the embedded silicide region. The net result is that a totally planar surface cannot be provided.
Ion implantation is also not a suitable technique for producing a buried epitaxial region that is planar with the semiconductor in which it is embedded. Using ion implantation, only very thin (.apprxeq.50 angstroms) epitaxial regions can be produced without requiring implantation over many days. Typically ion implantation is used when the implanted region is to be no more than about 1-10 monolayers deep.
Accordingly, it is a primary object of the present invention to provide a 3-dimensional semiconductor structure having embedded compounds therein which are epitaxial with both an underlying semiconductor layer and an overlying semiconductor layer.
It is another object of the present invention to provide a technique for producing 3-dimensional epitaxial semiconductor structures which are completely planar and include buried conductive regions in at least one of the semiconductor layers.
It is another object of this invention to provide a structure and technique for providing that structure, wherein the structure includes at least two epitaxial semiconductor layers which have located between them regions of conductive metal compounds of at least one of the semiconductors, where the top surface of the metal compound regions and the top surface of one of the semiconductor layers are substantially planar.
It is another object of the present invention to provide an epitaxial 3-dimensional structure comprised of two single crystal semiconductor layers wherein one of said semiconductor layers is single crystal silicon having embedded regions of a metal silicide therein, the top surface of the metal silicide regions being planar with the top surface of the silicon semiconductor layer in which the metal silicide regions are embedded.
It is another object of the present invention to provide a 3-dimensional epitaxial single crystal structure and method for making the structure wherein the same or different semiconductor layers can be used, there being a buried conductive epitaxial region between the two semiconductor layers.
It is another object of the present invention to provide a technique for making an epitaxial, 3-dimensional structure in which a first layer of single crystal silicon has embedded therein metal silicide regions whose top surface is planar with the top surface of the single crystal silicon, and an overlying layer of a material which is epitaxial with both the underlying silicon layer and the metal silicide regions.